1. Technical Field
The present invention relates to computer bus architecture. More specifically, the present invention relates to Inter Integrated Circuit (I2C) buses.
2. Description of Related Art
Many similarities exist between seemingly unrelated designs in consumer, industrial and telecommunication electronics. Examples of similarities include intelligent control, general-purpose circuits (i.e. LCD drivers, I/O ports, RAM) and application-oriented circuits. The Philips Inter Integrated Circuit (I2C) bus is a bi-directional two-wire serial bus designed to exploit these similarities.
Devices on the I2C bus are accessed by individual addresses, 00-FF (even addresses for Writes, odd addresses for reads). The I2C architecture can be used for a variety of functions. One example is Vital Product Data (VPD). Each component in the system contains a small Electrically Erasable Programmable Read Only Memory (EEPROM) (typically 256 bytes) which contains the VPD information such as serial numbers, part numbers, and EC revision level.
Normally, the device addresses on the I2C bus are predefined by hardwiring on the circuit boards. A limitation of the I2C bus is that it will only allow a single device to respond to each even address between 00 and FF. For this reason, most I2C devices must have a predefined address, which is typically assigned with the use of strapping pins on the device. For example, most I2C accessible EEPROMs have three strapping pins, which limit their addresses to A0-AF (even addresses only). Thus, only 8 devices can be connected to a single bus.
Therefore, a method for increasing the flexibility of the I2C bus system layout, by setting the device addresses in software, would be desirable.
The present invention provides a method, apparatus and program for dynamically allocating addresses to computer devices connected to Inter Integrated Circuit (I2C) buses. Upon resetting a I2C bus, the invention uses a bus driver to turn on the first bus switch on the bus. The invention then accesses the first device downstream of the switch and allocates a new value to the device""s address. The invention proceeds to turn on the next switch downstream. A new address is then allocated to the device downstream from the second switch. This process continues until all of the devices connected to the bus have unique addresses.